The Ultimate Desktop Motherboard Power Sequence Guide: From Pressing Power Button to POST
When you press the power button, the SIO pulls the PWRBTN# line low, notifying the PCH to initiate the power-up.
If Rail
| | Description | Access Level | |--------------|-----------------|------------------| | ATX Specification 2.x/3.x | Defines PSON#, PWR_OK timing, +5VSB requirements | Public | | Intel PCH Datasheet | Rail definitions, sequencing tables, SLP_Sx signals | NDA (some public excerpts) | | Intel EC Firmware Power Sequencing Module | EC handling of G3→S0 transitions and RSMRST# generation | Public (via GitHub) | | AMD Fusion Controller Hub Documentation | AMD-specific rail sequencing tables | Public summaries available | | Processor Power Sequencing Signals | Detailed PROCPWRGD, VCCST_PWRGD definitions | Public (Intel EDC) |
Once all power rails are stable, the system releases the reset signals (Platform Reset, ), allowing the CPU to start executing code from the BIOS. desktop motherboard power sequence pdf exclusive
The system is completely disconnected from AC power (e.g., the PSU switch is turned off or the wall plug is pulled).
If you need a breakdown of between the CPU and the VRM controller. Share public link The Ultimate Desktop Motherboard Power Sequence Guide: From
Powers the DDR memory modules and the memory controller interface.
Power sequencing is crucial for board bring-up because modern processors and chipsets have strict requirements about which voltages must appear before others — and within what time window. If you need a breakdown of between the